Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLS, RAM, and so forth).
The interconnect structure, CLBs, IOBs, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
One such FPGA, the Xilinx Virtex®-II FPGA, is described in detail in pages 33–75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.
FIG. 1 shows a typical FPGA architecture. The FPGA of FIG. 1 includes an array of logic blocks (e.g., CLBs 101a–101i) interconnected by a programmable interconnect structure. The interconnect structure includes interconnect lines (103a–103i, 104a–104i) coupled together by programmable switches (102a–102i).
One goal shared by many system designers is to obtain the highest operating frequency consistent with various design considerations including cost, power consumption, size, and so forth. Therefore, there is considerable motivation to provide fast programmable interconnect resources, as in the FPGA of FIG. 1. There are several known ways to improve the speed of programmable interconnect resources. One common method is to include interconnect lines of various lengths, e.g., spanning one CLB, two CLBs, six CLBs, half of the CLB array, and so forth. Another approach is to make some of the interconnect resources non-programmable, so the signals implemented using these resources do not traverse the programmable switches. Another method is to optimize the interconnect resources for speed by making the interconnect lines wider to reduce resistance, providing more space between interconnect lines to decrease coupling capacitance, and so forth.
However, each of these methods has a price in terms of increased silicon area, decreased routing flexibility, and so forth. Therefore, an approach has been suggested in which some interconnect resources are modified for higher speed while other interconnect resources are unmodified. For example, some interconnect lines can be wider and spaced further apart, while other interconnect lines use the minimum width and spacing supported by the manufacturing process.
FIG. 2 illustrates an FPGA designed using interconnect resources of two different speeds. The FPGA of FIG. 2 is similar to that of FIG. 1, except that the interconnect lines include both faster and slower interconnect lines.
Power consumption is often another concern of system designers. Power consumption can be a larger issue in programmable devices than in non-programmable devices. For example, in an FPGA each programmable switch has associated capacitance, which results in increased power dissipation. Further, FPGAs are consistently growing in size and supporting larger numbers of logic blocks. As the number of logic blocks in an FPGA increases, the numbers of interconnect resources required to service each logic block increases at a faster rate. Therefore, today's larger FPGAs have a higher percentage of silicon area devoted to interconnect resources than earlier, smaller FPGAs. Thus, the majority of the power dissipated in a modern FPGA is consumed by the programmable interconnect structure.
Therefore, it is desirable to provide an FPGA including a programmable interconnect structure in which fast interconnect resources are provided for critical signals, but which does not unnecessarily consume power.